ATMEGA649V-8MI【PDF 107/146 页】IC AVR MCU FLASH 64K 1.8V 64QFN

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2552K–AVR–04/11

ATmega329/3290/649/6490

If Timer/Counter2 and/or the LCD controller are enabled, they will keep running during sleep.

The device can wake up from either Timer Overflow or Output Compare event from

Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2,

and the Global Interrupt Enable bit in SREG is set. It can also wake up from an LCD controller

interrupt.

If neither Timer/Counter2 nor the LCD controller is running, Power-down mode is recommended

instead of Power-save mode.

The LCD controller and Timer/Counter2 can be clocked both synchronously and asynchronously

in Power-save mode. The clock source for the two modules can be selected independent of

each other. If neither the LCD controller nor the Timer/Counter2 is using the asynchronous

clock, the Timer/Counter Oscillator is stopped during sleep. If neither the LCD controller nor the

Timer/Counter2 is using the synchronous clock, the clock source is stopped during sleep. Note

that even if the synchronous clock is running in Power-save, this clock is only available for the

LCD controller and Timer/Counter2.

9.5

Standby Mode

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the

SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down

with the exception that the Oscillator is kept running. From Standby mode, the device wakes up

in six clock cycles.

9.6

Power Reduction Register

The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 40, pro-

vides a method to stop the clock to individual peripherals to reduce power consumption. The

current state of the peripheral is frozen and the I/O registers inaccessible. Resources used by

the peripheral when stopping the clock will remain occupied so the peripheral should be disabled

before stopping the clock. Waking up a peripheral, which is done by clearing the bit in PRR, puts

the peripheral in the same state as before shutdown.

Peripheral shutdown can be used in Idle mode and Active mode to reduce the overall power

consumption. In all other sleep modes, the clock is already stopped.

9.7

Minimizing Power Consumption

There are several possibilities to consider when trying to minimize the power consumption in an

AVR controlled system. In general, sleep modes should be used as much as possible, and the

sleep mode should be selected so that as few as possible of the device’s functions are operat-

ing. All functions not needed should be disabled. In particular, the following modules may need

special consideration when trying to achieve the lowest possible power consumption.

9.7.1

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 211

for details on ADC operation.

9.7.2

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,

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